library ieee;
use ieee.std_logic_1164.all;

entity Decodeur_tb is
end Decodeur_tb;

architecture tb of Decodeur_tb is
--passage de l'entité Decodeur au testbench comme composant
	component Decodeur is
	port(
	Entree: in std_logic_vector(1 downto 0);
	Sortie : out std_logic_vector(3 downto 0));
	end component;
	
	signal inE : std_logic_vector(1 downto 0);
	signal outS : std_logic_vector(3 downto 0);
begin
	--relier les signaux du testbench aux ports de Decodeur
	mapping: Decodeur port map(inE, outS);
	
	process
		--variable pour les erreurs
		variable errCnt : integer :=0;
	begin
		--TEST 1
		inE <= "00";
		wait for 15 ns;
		
		assert(outS = "0001") report "Error 1" severity error;
		if(outS /= "0001") then
			errCnt := errCnt +1;
		end if;
		
		--TEST 2
		inE <= "01";
		wait for 15 ns;
		
		assert(outS = "0010") report "Error 2" severity error;
		if(outS /= "0010") then
			errCnt := errCnt +1;
		end if;
		
		--TEST 3
		inE <= "10";
		wait for 15 ns;
		
		assert(outS = "0100") report "Error 3" severity error;
		if(outS /= "0100") then
			errCnt := errCnt +1;
		end if;
		
		--TEST 4
		inE <= "11";
		wait for 15 ns;
		
		assert(outS = "1000") report "Error 4" severity error;
		if(outS /= "1000") then
			errCnt := errCnt +1;
		end if;
	end process;
end architecture;