library ieee;
use ieee.std_logic_1164.all;

entity Registre_Nbits_tb is
end Registre_Nbits_tb;

architecture tb of Registre_Nbits_tb is

constant nbit : integer := 8;

component RegistreNbits is
generic(N:integer := nbit);
port(
	clk, load, reset: in std_logic;
	q: out std_logic_vector(N-1 downto 0);
	d: in std_logic_vector(N-1 downto 0)
	);
end component;

signal inL, inR : std_logic;
signal inD, outQ : std_logic_vector(nbit-1 downto 0);
signal  clock : std_logic := '1';

begin 
clock <= not clock after 5 ns;

mapping: RegistreNbits port map(clock, inL, inR, outQ, inD);

--inL <= '0','1' after 100 ns, '0' after 200 ns;

process 
variable errCnt : integer :=0;
begin
--TEST 1
inL <= '1';
inR <= '1';
inD <= "10101010";
wait for 15ns;
assert (outQ = "00000000") report "Error 1" severity error;
if(outQ /= "00000000") then
	errCnt := errCnt +1;
end if;

--TEST 2
inL <= '1';
inR <= '0';
ind <= "10101010";
wait for 15ns;
assert (outQ = "10101010") report "Error 2" severity error;
if(outQ /= "10101010") then
	errCnt := errCnt +1;
end if;

inR <= '1';
wait for 15ns;

--TEST 3
inL <= '0';
inR <= '0';
ind <= "10101010";
wait for 15ns;
assert (outQ = "00000000") report "Error 3" severity error;
if(outQ /= "00000000") then
	errCnt := errCnt +1;
end if;


end process;

end architecture tb;