library ieee;
use ieee.std_logic_1164.all;

entity RegistreNbits is
generic(N:integer := 8);
port(
	clk, load, reset: in std_logic;
	q: out std_logic_vector(N-1 downto 0);
	d: in std_logic_vector(N-1 downto 0)
	);
end RegistreNbits;

architecture arch of RegistreNbits is
begin
	process(clk)
	begin
	if(rising_edge(clk)) then
		if (reset = '1') then
			q <= (others => '0');
		elsif (load = '1') then --rising_edge(clk)
			q <= d;
		end if;
	end if;	
	end process;
end arch;