library ieee;
use ieee.std_logic_1164.all;
entity soustracteur is
port
(
a,b,cin  : in  std_logic;
s,cout   : out std_logic);
end soustracteur;
--

architecture archConc of soustracteur is 
signal bn :std_logic;
begin
bn   <= not b;
s    <= a xor bn xor cin;
cout <= (a and bn) or (a and cin) or (bn and cin);
end archConc;