library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity additionneur_numericstd is
port	(
		-- Input ports
		a,b	: in  std_logic_vector(3 downto 0);
		cin : in std_logic;

		-- Output ports
		s : out std_logic_vector(3 downto 0);
		cout : out std_logic
	);
end additionneur_numericstd;

architecture add_num of additionneur_numericstd is

signal s_int : unsigned(4 downto 0);
signal cin_nat  : natural range 0 to 1;
signal t : std_logic_vector (4 downto 0);
begin
	cin_nat <= 1 when cin='1' else 0;
	s_int <= unsigned('0' & a) + unsigned('0' & b) + cin_nat;
	s <= std_logic_vector(s_int(3 downto 0));
	cout <= s_int(4);
end add_num;