library ieee;
use ieee.std_logic_1164.all;

entity additionneur4 is
	port
	(
		-- Input ports
		a,b	: in  std_logic_vector(3 downto 0);
		cin : in std_logic;

		-- Output ports
		s : out std_logic_vector(3 downto 0);
		cout : out std_logic
	);
end additionneur4;


-- Library Clause(s) (optional)
-- Use Clause(s) (optional)

architecture arch_add4 of additionneur4 is

	-- Declarations (optional)
	
	component additionneur is
	
	port
	(
	a,b,cin  : in  std_logic;
   s,cout   : out std_logic
	);
	end component;
	
	signal s0to1, s1to2, s2to3 : std_logic;

begin

	-- Process Statement (optional)

	-- Concurrent Procedure Call (optional)

	-- Concurrent Signal Assignment (optional)

	-- Conditional Signal Assignment (optional)

	-- Selected Signal Assignment (optional)

	-- Component Instantiation Statement (optional)
	a0	: additionneur
	port map
	(
	a => a(0),
	b => b(0),
	s => s(0),
	cin => cin,
	cout => s0to1
	);
	
	a1	: additionneur
	port map
	(
	a => a(1),
	b => b(1),
	s => s(1),
	cin => s0to1,
	cout => s1to2
	);
	
	a2	: additionneur
	port map
	(
	a => a(2),
	b => b(2),
	s => s(2),
	cin => s1to2,
	cout => s2to3
	);
	
	a3	: additionneur
	port map
	(
	a => a(3),
	b => b(3),
	s => s(3),
	cin => s2to3,
	cout => cout
	);
	
	
	-- Generate Statement (optional)

end arch_add4;