library ieee;
use ieee.std_logic_1164.all;

entity ALU_tb is
end ALU_tb;

architecture tb of ALU_tb is

	component ALUv1 is
port	(
		-- Input ports
		a,b : in std_logic_vector(7 downto 0);
	   op : in std_logic_vector (2 downto 0);
		cin : in std_logic;

		-- Output ports
		s : out std_logic_vector(7 downto 0);
		cout : out std_logic
	);
	end component;
	
	signal inOP : std_logic_vector(2 downto 0);
	signal inA, inB : std_logic_vector(7 downto 0);
	signal outS : std_logic_vector(7 downto 0);
	signal inC : std_logic;
	signal outC : std_logic;
	
begin
	--relier les signaux du testbench aux ports de Decodeur
	mapping: ALU_tb port map(inA, inB, inOP, inC, outS, outC);
	
	process
		--variable pour les erreurs
		variable errCnt : integer :=0;
	begin
		--TEST 1
		inA <= "00000001";
		inB <= "00000010";
		inOP <= "000";
		wait for 15 ns;
		assert(outS = "00000011") report "Error 1" severity error;
		assert(outC = "0") report "Error 1" severity error;
		if(outS /= "00000011" or outC /= "0") then
			errCnt := errCnt +1;
		end if;
		
		--TEST 2
		inA <= "11111111";
		inB <= "00000001";
		inOP <= "000";
		wait for 15 ns;
		assert(outS = "00000000") report "Error 1" severity error;
		assert(outC = "1") report "Error 1" severity error;
		if(outS /= "00000000" or outC /= "1") then
			errCnt := errCnt +1;
		end if;
		

	end process;
end architecture;