library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALUv1 is
port	(
		-- Input ports
		a,b : in std_logic_vector(7 downto 0);
	   op : in std_logic_vector (2 downto 0);
		cin : in std_logic;

		-- Output ports
		s : out std_logic_vector(7 downto 0);
		cout : out std_logic
	);
end ALUv1;

architecture Arch_alu1 of ALUv1 is

signal s_int : unsigned(8 downto 0);
signal cin_nat  : natural range 0 to 1;
signal t : std_logic_vector (8 downto 0);

begin process(all)
begin case op is
when "000" => --ADD
if cin='1' then cin_nat <= 1; else cin_nat <= 0; end if;
s_int <= unsigned('0' & a) + unsigned('0' & b) + cin_nat;
s <= std_logic_vector(s_int(7 downto 0));
cout <= s_int(8);
when "001" => --SUB
if cin='1' then cin_nat <= 1; else cin_nat <= 0; end if;
s_int <= unsigned('0' & a) - unsigned('0' & b) + cin_nat;
s <= std_logic_vector(s_int(7 downto 0));
cout <= s_int(8);
when "010" => --AND
s_int <= unsigned('0' & a) AND unsigned('0' & b) + cin_nat;
s <= std_logic_vector(s_int(7 downto 0));
when "011" => --OR
s_int <= unsigned('0' & a) OR unsigned('0' & b) + cin_nat;
s <= std_logic_vector(s_int(7 downto 0));
when "100" => --XOR
s_int <= unsigned('0' & a) XOR unsigned('0' & b) + cin_nat;
s <= std_logic_vector(s_int(7 downto 0));
WHEN OTHERS => NULL;
end case;
end process;

end architecture Arch_alu1;